1. Field of the Invention
The present invention relates to integrated circuit memory devices, and to sense circuitry in such memory devices.
2. Description of Related Art
Integrated circuit memory devices are becoming smaller and faster. One limitation on the size and speed of memory devices arises from circuitry used for precharging and biasing bit lines in preparation for sensing data from the array. Typical structures used for these purposes are illustrated in U.S. Pat. No. 6,219,290, entitled MEMORY CELL SENSE AMPLIFIER, invented by Chang et al.; U.S. Pat. No. 6,498,751, entitled FAST SENSE AMPLIFIER FOR NONVOLATILE MEMORIES, invented by Ordonez, et al.; and U.S. Pat. No. 6,392,447, entitled SENSE AMPLIFIER WITH IMPROVED SENSITIVITY, invented by Rai et al.
FIG. 1 illustrates a basic biasing structure used in prior art memory devices. The memory devices include a plurality of sense amplifiers, such as sense amplifiers 22, 23, 24 and 25. In the illustrated system, sense amplifier 22 has a first input coupled to bit line BL0 and a second input coupled to a reference voltage on line 26. Sense amplifier 23 has a first input coupled to bit line BL1 and a second input coupled to a reference voltage on line 27. Sense amplifier 24 has a first input coupled to bit line BL2 and a second input coupled to a reference voltage on line 28. Sense amplifier 25 has a first input coupled to bit line BL127 and a second input coupled to a reference voltage on line 29. As shown, a number of sense amplifiers, such as 8, 16, 32, 64, the illustrated 128, or more, for sensing a number of bits of data in parallel from a memory array are provided. Decoding circuitry, not shown, is used to select, from among thousands of columns of memory cells in a typical integrated circuit memory device, columns of memory cells for connection to the bit lines in response to addressing. In FIG. 1, memory cell 30 is shown coupled to bit line BL0, memory cell 31 is shown coupled to bit line BL1, memory cell 32 is shown coupled to bit line BL2 and memory cell 33 is shown coupled to bit line BL127. A capacitance CBL is illustrated in the figure, which represents the total bit line capacitance for a path on the bit line BL0 to a selected memory cell on a selected column in the memory array. The voltage on the bit line VBL, is established by charging the bit line capacitance CBL with current through the load transistors 14–17.
Each of the bit lines BL0, BL1, BL2, . . . BL127 includes a biasing structure used to bias the bit line in preparation for sensing. The biasing structure in the illustrated embodiment for the bit line BL0 comprises a clamp transistor 10 and a load transistor 14. Clamp transistor 11 and load transistor 15 are coupled with bit line BL1. Clamp transistor 12 and load transistor 16 are coupled with bit line BL2. Clamp transistor 13 and load transistor 17 are coupled with bit line BL127. The load transistors 14–17 in the illustrated embodiment comprise respective n-channel MOS transistors having their gates and drains coupled to a supply potential VDD, and sources coupled to a sensing node (labeled VCELL at the sense amplifier inputs) on the respective bit lines. The clamp transistors 10–13 comprise respective n-channel MOS transistors having drains coupled to the sensing nodes (VCELL), sources coupled to conductors that are coupled via decoding circuitry to the selected memory cells in the array, and gates coupled to the output of respective feedback inverters 18–21. The inputs to the feedback inverters 18–21 are coupled to the sources of the clamp transistors 10–13 and to the conductors that are coupled via decoding circuitry to the selected memory cells in the array.
In the operation, the load transistors and clamp transistors maintain the sensing node at a level designed to match the sense amplifier operation, and to allow fast sensing. Thus, the sensing node is maintained at a level usually just above the reference voltage (labeled VREF at the sense amplifier inputs). With reference to bit line BL0, as the voltage VBL on the bit line BL0 at the source of the clamp transistor 10 reaches a level at the trigger point of the feedback inverter 18, the output of the feedback inverter 18 starts to go down, and begins to turn off the clamp transistor 10, which reduces current flow and tends to allow the voltage on the source of the clamp transistor 10 to stop rising, or go down. An equilibrium condition is established on the bit line BL0 by this dynamic feedback, with a small current through the load transistor 14. The voltage at the sensing node VCELL settles at the target level, and the bit line is ready for sensing. After the interval allowing the voltage at the sensing node to settle at the target level, the memory cell is accessed for sensing by applying a word line potential to the gate of the memory cell, for example, on a selected word line. If the memory cell turns on in response to the voltage applied on its gate, then the voltage on the sensing node will be pulled down below the reference voltage VREF. On the other hand, if the memory cell does not turn on in response to the voltage applied on its gate, then the voltage on the sensing node will not be pulled down. The sense amplifier determines how the voltage on the sensing node behaves and generates an output signal indicating the value of the data stored in the memory cell.
In an alternative embodiment known in the prior art, as shown in FIG. 2, the dynamic feedback inverters are replaced with a simple bias voltage VBIAS. Thus, the embodiment shown in FIG. 2 includes load transistor 40 and clamp transistor 41, which are arranged like load transistor 14 and clamp transistor 10 of FIG. 1. The bias voltage VBIAS is produced by a reference voltage circuit, and applied to the gate of the clamp transistor 41. The source of the clamp transistor 41 is coupled to a selected memory cell through decoding circuitry not shown. The bit line capacitance is represented by the capacitor CBL as discussed above with respect to FIG. 1. The sensing node between the load transistor 40 and the clamp transistor 41 is coupled to a sense amplifier 42. The circuit in FIG. 2 operates in a manner similar to that described above with respect to FIG. 1, without the dynamic feedback. As the voltage VBL on the bit line reaches a level that is about a threshold voltage drop across the clamp transistor 41 below the bias voltage VBIAS, the clamp transistor 41 begins to turn off and reduce current flow. The dynamic balance is achieved with the voltage at the sensing node VCELL settling on a target value. At this point, the precharge step is completed, and the bit line is ready for sensing. Upon accessing a memory cell, the cell data influences the voltage at the node VCELL, causing it to move quickly toward a high cell threshold value VCELL—HVT or toward a low cell threshold value VCELL—LVT. The reference voltage VREF applied to the sense amplifier 42 is set at a value about halfway between VCELL—HVT and VCELL—LVT. The margin between the target value on VCELL and VREF at the sense amplifier 42 is large enough to cover noise effects, but as small as possible for quick sensing.
The time required for the voltage on the sensing node to settle at its target level has limited the speed of such sensing systems. Thus, precharging techniques have been provided such as shown in FIG. 3, which apply a higher current during the process of raising the bit line voltage VBL to establish the target level at the sensing node. In the prior art embodiment of FIG. 3, a bit line is coupled to a selected memory cell 53 by decoding circuitry not shown. The clamp transistor 51 on the bit line is connected to the sensing node VCELL. A load 50 (such as the diode connected transistor shown in FIG. 1 and FIG. 2, but also other types of loads could be provided), is connected between the sensing node VCELL and a supply potential VDD. Sense amplifier 52 is coupled to the sensing node VCELL and a reference voltage VREF, as described above. The gate of the clamp transistor 51 is connected to bias voltage VBIAS like that described with reference to FIG. 2. In an alternative system, a dynamic feedback inverter, connected as shown in FIG. 1, is used to bias the gate of the clamp transistor 51. Additional precharge current is provided through transistor 54 and transistor 55. Transistor 54 is an n-channel MOS transistor having its source coupled to the source of clamp transistor 51, and its gate coupled to the gate of clamp transistor 51 so that it receives the same bias voltage VBIAS (or the same output of the feedback inverter). Transistor 55 is a p-channel MOS transistor having its drain coupled to the drain of transistor 54, its source coupled to a precharge supply voltage, which is typically, although not necessarily, the same supply voltage as the load supply voltage VDD. The gate of the transistor 55 is controlled by a logic signal PRE, which enables precharging when it is at a low level, by turning on transistor 55 into saturation with consequently very little voltage drop across it. Transistor 54 is a transistor having a higher threshold voltage than the clamp transistor 51. The higher threshold is achieved for example by making transistor 54 with a narrower and longer channel region. Therefore, during a precharge interval precharge paths are provided both through the load 50 and the transistor 55. Both transistors 54 and 51 will be on while the voltage on the bit line VBL is low. As the voltage on the bit line VBL approaches VBIAS (less the threshold of transistor 54, including body effects), transistor 54 will turn off first because of its higher threshold voltage, and disable the precharge path through transistor 55. Dynamic balance will be achieved between the load 50 and the clamp transistor 51 as described above, settling the sensing node at the target level. Because the path through transistor 55 is enabled during the first part of the precharge operation, more current is applied to charging up the bit line capacitance CBL, and the voltage on the bit line VBL rises more quickly. Thus, the sensing system settles on the target voltage more quickly. With a shorter precharge interval, faster sensing can be achieved.
While these prior art techniques have been applied for memory devices successfully, as memory access speeds increase, component sizes decrease, and more complicated and more highly parallel sensing structures are deployed, the requirement of complex biasing structures on every bit line is becoming a limiting factor on size and cost of integrated circuit memories. It is therefore desirable to provide sensing systems that occupy less space on an integrated circuit, operate faster and consume less power.